![]() Next, the SHIFT/LD\’ goes low enabling loading of data as opposed to shifting of data. ![]() As an example we present 101 to the parallel inputs D AA D BB D CC. What we previously described with words for parallel loading and shifting is now set down as waveforms above. Parallel data at D A D B D C is converted to serial data at SO. The waveforms below show both parallel loading of three bits of data and serial shifting of this data. Clock pulses will cause data to be right shifted out to SO on successive pulses. The lower AND gates of the pairs feeding the OR gate are enabled giving us a shift register connection of SI to D A , Q A to D B , Q B to D C , Q C to SO. The shift path is shown above when SHIFT/LD\’ is logic high. ![]() Only one of these load methods is used within an individual device, the synchronous load being more common in newer devices. This needs to be differentiated from asynchronous load where loading is controlled by the preset and clear pins of the Flip-Flops which does not require the clock. The type of parallel load just described, where the data loads on a clock pulse is known as synchronous load because the loading of data is synchronized to the clock. Three bits of data will load into Q A Q B D C at the same time. At the next positive going clock edge, the data will be clocked from D to Q of the three FFs. The upper NAND gates serving D A D B D C are enabled, passing data to the D inputs of type D Flip-Flops Q A Q B D C respectively. Four, eight or sixteen bits is normal for real parts.Ībove we show the parallel load path when SHIFT/LD\’ is logic low. We show three stages due to space limitations. In general, these elements will be replicated for the number of stages required. A stage consists of a type D Flip-Flop for storage, and an AND-OR selector to determine whether data will load in parallel, or shift stored data to the right. By serial format we mean that the data bits are presented sequentially in time on a single wire or circuit as in the case of the “data out” on the block diagram below.īelow we take a close look at the internal details of a 3-stage parallel-in/ serial-out shift register. This is a way to convert data from a parallel format to a serial format.īy parallel format we mean that the data bits are present simultaneously on individual wires, one for each data bit as shown below. In addition, parallel-in/ serial-out really means that we can load data in parallel into all stages before any shifting ever begins. The parallel-in/ serial-out shift register stores data, shifts it on a clock by clock basis, and delays it by the number of stages times the clock period. Parallel-in/ serial-out shift registers do everything that the previous serial-in/ serial-out shift registers do plus input data to all stages simultaneously. ![]()
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